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19-2132; Rev 0; 8/01
Low-Power, Low-Glitch, Octal 12-Bit VoltageOutput DACs with Serial Interface
General Description
The MAX5306/MAX5307 are 12-bit, eight channel, lowpower, voltage-output, digital-to-analog converters (DACs) in a space-saving 16-pin TSSOP package. The wide +2.7V to +5.5V supply voltage range and less than 215A (max) supply current per DAC are excellent for low-power and low-voltage applications. The low 2nV/s glitch energy of the MAX5306/MAX5307 makes them ideal for digital control of fast-response, closedloop systems. The MAX5306 has a digital output (DOUT) that can be used for daisy-chaining multiple devices. The MAX5307 has a hardware reset input (CLR) which clears all registers and DACs to zero. The MAX5306/MAX5307 have a software shutdown feature that reduces the supply current to 1A. The MAX5306/MAX5307 feature a load DAC (LDAC) function that updates the output of all eight DACs simultaneously. The 3-wire SPITM, QSPITM, MICROWIRETM and DSPcompatible serial interface allows the input and DAC registers to be updated independently or simultaneously with a single software command. These devices use a double-buffered design to minimize the digital-noise feedthrough from the digital inputs to the outputs. The MAX5306/MAX5307 operating temperature range is from -40C to +85C.
Features
o Eight Highly Integrated 12-Bit DACs in 16-Pin TSSOP (6.4mm x 5mm) Package o Ultra-Low Glitch Energy <2nV/s o Low Total Supply Current: 1.7mA (max) with VREF = VDD = +5.5V o +2.7V to +5.5V Wide Single-Supply Range o Fast 5s Settling Time o Software-Selectable Shutdown Mode < 1A o 15MHz 3-Wire SPI, QSPI, and MICROWIRECompatible Serial Interface o Power-Up Reset to Zero Scale
MAX5306/MAX5307
Ordering Information
PART MAX5306EUE MAX5307EUE TEMP. RANGE -40C to +85C -40C to +85C PIN-PACKAGE 16 TSSOP 16 TSSOP
Applications
Gain and Offset Adjustment Power Amplifier Control Process Control I/O Boards Portable Instrumentation Equipment Control of Optical Components
TOP VIEW
SCLK 1 DIN 2 LDAC 3 REF 4 OUT1 5 OUT2 6 OUT3 7 OUT4 8
Pin Configuration
16 CS 15 DOUT (CLR) 14 VDD
MAX5306 MAX5307
13 GND 12 OUT8 11 OUT7 10 OUT6 9 OUT5
16-TSSOP
() FOR MAX5307 ONLY
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp.
________________________________________________________________ Maxim Integrated Products
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Low-Power, Low-Glitch, Octal 12-Bit VoltageOutput DACs with Serial Interface MAX5306/MAX5307
ABSOLUTE MAXIMUM RATINGS
VDD to GND ............................................................. -0.3V to +6V All Other Pins to GND.................................-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP (derate 9.4mW/C above +70C) .........775mW Maximum Current Into Any Pin .........................................50mA Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, CL = 200pF, RL = 2k, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25C.)
PARAMETER STATIC ACCURACY (Notes 1, 2) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error (Note 3) Offset Error Temperature Coefficient Gain Error (Note 3) Gain Error Temperature Coefficient REFERENCE INPUT Reference Input Voltage Range (Note 4) Reference Input Impedance Reference Current DAC OUTPUTS Output Voltage Range DC Output Impedance Capacitive Load Resistive Load Short-Circuit Current Wake-Up Time CL RL VDD = +5V VDD = +2.7V From shutdown mode With no load 0.020 0.5 500 2 33 20 24 VDD 0.020 V pF k mA s VREF RREFIN IREFPD In power-down mode 0.8 135 200 1 VDD 265 10 V k A VGE N INL DNL VOE Guaranteed monotonic 10 10 0.1 5 1 12 1 4 1.0 60 Bits LSB LSB mV V/C % of FS ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Low-Power, Low-Glitch, Octal 12-Bit VoltageOutput DACs with Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, CL = 200pF, RL = 2k, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5306/MAX5307
DIGITAL INPUTS (SCLK, DIN, CS, LDAC, CLR-MAX5307) VDD = +5V 10% Input High Voltage VIH VDD = +3V 10% VDD = +5V 10% Input Low Voltage Input Leakage Current Input Capacitance DIGITAL OUTPUT (MAX5306) Output Low Voltage Output High Voltage DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time Digital Feedthrough DAC Glitch Impulse DAC Output Noise DAC to DAC Crosstalk POWER REQUIREMENTS Supply Voltage Range VDD All digital inputs at 0 or VDD, VDD = VREF = +5.5V Supply Current with No Load (Note 5) IDD All digital inputs at 0 or VDD, VDD = +5.5V, VREF = +1.2V All digital inputs at 0 or VDD, VDD = VREF = +3V Shutdown mode 2.7 1.5 1.1 1.3 1 10 A 5.5 1.7 1.3 mA V SR tS Positive and negative 400hex to C00hex Code 0, all digital inputs from 0V to VDD Major carry transition 1 5 0.5 2 600 0.5 V/s s nV/s nV/s Vp-p nV/s VOL VOH ISINK = 1mA ISOURCE = 1mA VDD 0.5 0.5 V V VIL VDD = +3V 10% IIN CIN All digital inputs 0 or VDD 0.1 10 0.6 10 A pF 2.4 V 2.1 0.8 V
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Low-Power, Low-Glitch, Octal 12-Bit VoltageOutput DACs with Serial Interface MAX5306/MAX5307
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, CL = 200pF, RL = 2k, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25C.)
PARAMETER TIMING CHARACTERISTICS Serial Clock Frequency SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Fall Setup Time SCLK Fall to CS Rise Setup Time LDAC Pulse Width Low CLR Pulse Width Low DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time CS Pulse Width High SCLK Rise to DOUT Fall SCLK Rise to DOUT Rise fSCLK tCH tCL tCSS tCSH tLDACPWL tCLRPWL tDS tDH tCSPWH tSDL tSDH Load capacitance = 20pF Load capacitance = 20pF MAX5307 only 0 33 33 16 20 20 20 16 10 20 50 50 15 MHz ns ns ns ns ns ns ns ns ns ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: Note 2: Note 3: Note 4: Note 5:
Static accuracy tested without load. Linearity is tested within codes 73hex to F8Dhex. Gain and offset tested within codes 73hex to F8Dhex. Static accuracy specifications valid for VREF = 1.2V to VDD. Current scales linearly between these two extremes of VREF.
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Low-Power, Low-Glitch, Octal 12-Bit VoltageOutput DACs with Serial Interface
Typical Operating Characteristics
(VDD = +5V, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5306 toc01
MAX5306/MAX5307
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5306 toc02
REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
0 RELATIVE OUTPUT (dB)
MAX5306 toc03
1.000 0.800 0.600 0.400 0.200 0 -0.200 -0.400 0 1000 2000 3000 4000 DIGITAL INPUT CODE
0.300 0.200 0.100 DNL (LSB) 0
-5
INL (LSB)
-10
-0.100 -0.200 -0.300 0 1000 2000 3000 4000
-15 VREF SWEPT 1Vp-p RL = 2k, CL = 200pF -20 0 100 200 300 400 500 FREQUENCY (kHz)
DIGITAL INPUT CODE
SUPPLY CURRENT vs. TEMPERATURE
MAX5306 toc04
SUPPLY CURRENT vs. REFERENCE VOLTAGE
MAX5306 toc05
SUPPLY CURRENT vs. SUPPLY VOLTAGE
TA = -40C 0.95 SUPPLY CURRENT (mA) 0.90 0.85 0.80 TA = +85C 0.75 0.70 VREF = +1.2V CODE = 000 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) TA = +25C
MAX5306 toc06 MAX5306 toc09
1.105 1.100 SUPPLY CURRENT (mA) 1.095 1.090 1.085 1.080 1.075 1.070 1.065 1.060 -40 -20 0 20 40 60 80 TEMPERATURE (C) VREF = +2.5V CODE = 000
1.3 1.2 SUPPLY CURRENT (mA) 1.1 1.0 0.9 0.8 0.7 0.6 VDD = +3V VDD = +5V
1.00
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 REFERENCE VOLTAGE (V)
SUPPLY CURRENT VS. SUPPLY VOLTAGE (CODE = FFFHEX)
MAX5306 toc07
SOURCE-AND-SINK CURRENT CAPABILITY
6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 5 VDD = VREF = +5V CODE = FFFHEX, SOURCING CURRENT FROM OUT_
MAX5306 toc08
FULL-SCALE ERROR vs. REFERENCE VOLTAGE
0 -1 FULL-SCALE ERROR (LSB) -2 -3 -4 -5 -6 -7 -8 -9 VDD = +5V, CODE = FFFHEX NORMALIZED TO VREF = +5V
1.80 1.75 SUPPLY CURRENT (mA) TA = +25C 1.70 1.65 1.60 1.55 1.50 TA = -40C
VOUT (V)
TA = +85C
CODE = C00HEX, SOURCING CURRENT FROM OUT_ CODE = 400HEX, SINKING CURRENT INTO OUT_ CODE = 000HEX, SINKING CURRENT INTO OUT_ 10 15 20 ISOURCE/SINK (mA) 25 30
VREF = 1.2V CODE = FFFHEX 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V)
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Low-Power, Low-Glitch, Octal 12-Bit VoltageOutput DACs with Serial Interface MAX5306/MAX5307
Typical Operating Characteristics (continued)
(VDD = +5V, TA = +25C, unless otherwise noted.)
FULL-SCALE ERROR vs. LOAD CURRENT
MAX5306 toc10
REFERENCE FEEDTHROUGH AT 1kHz, RL = 2k, CL = 200pF
MAX5306 toc11
DAC-TO-DAC CROSSTALK
MAX5306 toc12
0 -1 FULL-SCALE ERROR (LSB) -2 -3 -4 -5 -6 -7 0.1 1 LOAD CURRENT (mA) VREF = +4.096V NORMALIZED TO 0.1mA
REF, 2V/div
OUT1 2V/div
O OUT2 AC-COUPLED 10mV/div OUT_ 1mVp-p CODE = 000 10 400s 10s/div
DYNAMIC RESPONSE
MAX5306 toc13
MAJOR-CARRY TRANSITION
MAX5306 toc14
DIGITAL FEEDTHROUGH (SCLK = 1.4MHz)
MAX5306 toc15
OUT_ 1V/div
CS 5V/div
SCLK 2V/div
O
OUT_ AC-COUPLED 5mV/div
OUT_ AC-COUPLED 5mV/div
10s/div VREF = +2.5V, RL = 2k, CL = 200pF SWITCHING FROM CODE 000HEX TO FFFHEX
4s/div VREF = +2.5V, RL = 2k, CL = 200pF
400ns/div VREF = +2.5V, RL = 2k, CL = 200pF CS = +5V, DIN = 0 DAC CODE SET to 800HEX
NEGATIVE FULL-SCALE SETTLING TIME
MAX5306 toc16
POSITIVE FULL-SCALE SETTLING TIME
MAX5306 toc17
OUT_ 500mV/div
OUT_ 500mV/div
O
O
1s/div
1s/div
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Low-Power, Low-Glitch, Octal 12-Bit VoltageOutput DACs with Serial Interface
Pin Description
PIN 1 2 3 4 5-12 13 14 15 16 NAME SCLK DIN LDAC REF OUT_ GND VDD DOUT CLR CS Serial Data Input Load DAC. LDAC is an asynchronous active-low input that updates the DAC outputs simultaneously. If LDAC is driven low, the DAC registers are transparent. Reference Voltage Input Analog Output Signal Ground Power Supply. Bypass VDD to GND with a 0.1F capacitor. Data Output (MAX5306). DOUT is updated on the falling edge of SCLK. Asynchronous Clear DAC (MAX5307). Active-low input to clear all DACs and registers. Resets all outputs to zero. Chip-Select Input (active-low) FUNCTION Serial Clock Input. Serial data is loaded on the falling edge of SCLK.
MAX5306/MAX5307
Detailed Description
The MAX5306/MAX5307 are 12-bit, eight-channel, lowpower, voltage-output digital-to-analog converters (DACs) that are easily addressed using a simple 3-wire serial interface. These devices feature eight doublebuffered DACs using a common 16-bit serial to parallel shift register, a power-on reset (POR) circuit and eight output buffer amplifiers. Figure 1 shows the block diagram of MAX5306/ MAX5307. The shift register converts a serial 16-bit word to parallel data for each input register operating with a clock rate of up to 15MHz. The 3-wire digital interface to the shift register consist of chip-select (CS), serial clock (SCLK), and data input (DIN). Serial data at DIN is loaded on the falling edge of SCLK. The eight double-buffered DACs consist of input and DAC registers. The input registers are directly connected to the shift register and hold the result of the most recent write operation. The eight 12-bit DAC registers hold the current output code for the respective DAC. Data can be transferred from the input registers to the DAC registers by either the hardware interface (LDAC) or by software command. The output of DACs are buffered through eight Rail-to-Rail(R) op amps. The MAX5306 has a digital output (DOUT) which can be used to daisy chain multiple devices on a single serial bus. The MAX5307 contains a hardware shutdown (CLR) to clear all internal registers and power-down all DACs.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
The MAX5306/MAX5307 require an external reference such as the MAX6161 family. The reference voltage range is from 0.8V to VDD. POR circuitry gives the DACs a defined state during startup. At power-on, the DAC outputs reset to zero through a 100k resistor, providing additional safety for applications that drive valves or other transducers that need to be off at power-up. The MAX5306/MAX5307 feature low digital feedthrough and minimize glitch energy on MSB transitions. The 3wire SPI, QSPI, MICROWIRE and DSP-compatible serial interface saves additional circuit board space .
Serial Interface Configuration
The MAX5306/MAX5307 3-wire serial interface are compatible with MICROWIRE, SPI, QSPI, and DSPs (Figure 2 and Figure 3). The chip-select input (CS) frames the serial data loading at DIN. Following CS's high-to-low transition, the data is shifted synchronously and latched into the input register on each falling edge of the serial clock input (SCLK). Each serial word is 16 bits, the first four bits are the control word followed by 12 data bits (MSB first) as shown in Table 1. The 12-bit DAC code is unipolar binary with 1LSB = VREF/4096. The serial input register transfers its contents to the input registers after loading 16 bits of data and driving CS high. CS must be brought high for a minimum of 20ns before the next write sequence since a write
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Low-Power, Low-Glitch, Octal 12-Bit VoltageOutput DACs with Serial Interface MAX5306/MAX5307
Table 1. Serial Interface Configuration
16-BIT SERIAL WORD CONTROL BITS MSB 0 0 0 0 X X X X X X X X X X X DATA BITS LSB X DESC. FUNCTION
C3 C2 C1 C0 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 NOP No Operation RESET All Internal Registers. Power-down DACs, outputs pulled down with 100k. Equivalent to software CLR. D11-D0 to Input Register 1, DAC Output Unchanged D11-D0 to Input Register 2, DAC Output Unchanged D11-D0 to Input Register 3, DAC Output Unchanged D11-D0 to Input Register 4, DAC Output Unchanged D11-D0 to Input Register 5, DAC Output Unchanged D11-D0 to Input Register 6, DAC Output Unchanged D11-D0 to Input Register 7, DAC Output Unchanged D11-D0 to Input Register 8, DAC Output Unchanged
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
RESET
0 0 0 0 0 0 1 1
0 0 1 1 1 1 0 0
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6 DAC 7 DAC 8
1
0
1
0
D11-D0 to Input Registers DAC 1-4 1-4 and DAC Registers 1-4, DAC Outputs Updated (Write-Thru). D11-D0 to Input Registers DAC 5-8 and DAC Registers, DAC Outputs Updated (Write-Thru). D11-D0 to Input Registers DAC 1-8 and DAC Registers, DAC Outputs Updated (Write-Thru). DAC 1-8 D11-D0 to Input Registers, DAC Outputs Unchanged
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
DAC DAC DAC DAC DAC DAC DAC DAC 8 7 6 5 4 3 2 1
X
X
X
X
Input Registers to DAC Registers Indicated by Ones, DAC Outputs DAC 1-8 Updated, Equivalent to Software LDAC (No effect on DACs indicated by 0's.)
X = Don't Care 8 _______________________________________________________________________________________
Low-Power, Low-Glitch, Octal 12-Bit VoltageOutput DACs with Serial Interface MAX5306/MAX5307
VDD
MAX5306 MAX5307
CS
INPUT REGISTER 1
DAC REGISTER
DAC 1
OUT1
SCLK SERIAL TO PARALLEL SHIFT REGISTER DIN
INPUT REGISTER 2
DAC REGISTER
DAC 2
OUT2
INPUT REGISTER 3
DAC REGISTER
DAC 3
OUT3
(MAX5307) CLR
INPUT REGISTER 4
DAC REGISTER
DAC 4
OUT4
(MAX5306) DOUT
INPUT REGISTER 5
DAC REGISTER
DAC 5
OUT5
INPUT REGISTER 6
DAC REGISTER
DAC 6
OUT6
INPUT REGISTER 7
DAC REGISTER
DAC 7
OUT7
INPUT REGISTER 8
DAC REGISTER
DAC 8
OUT8
LDAC GND REF
Figure 1. Functional Block Diagram
sequence is initiated on a falling edge of CS. If CS goes high prior to completing 16 cycles of SCLK, the input data is discarded. To initiate a new data transfer, drive CS low again. The serial clock (SCLK) can be either high or low between CS write pulses. Figure 4 shows the timing diagram for the complete 3-wire serial interface transmission. The MAX5306/MAX5307 digital inputs are doublebuffered. Depending on the command issued through
the serial interface, the input register(s) can be loaded without affecting the DAC register(s), the DAC register(s) can be loaded directly, or all eight registers can be updated simultaneously from the input registers.
Shutdown Modes
The MAX5306/MAX5307 include three software-controlled shutdown modes that reduce the supply current to less than 1A. In two of the three shutdown modes (shutdown 2 and 3) the outputs are independently con9
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Low-Power, Low-Glitch, Octal 12-Bit VoltageOutput DACs with Serial Interface MAX5306/MAX5307
Table 2. Serial Interface Power-up and Power-down Commands
CONTROL BITS C3 C2 C1 DATA BITS FUNCTION DESC. DAC DAC DAC DAC DAC DAC DAC DAC D03 D02 D01 D00 C0 8 7 6 5 4 3 2 1
1
1
1
1
1
1
X
X
Power-Up individual DAC buffers indicated by data in Power- DAC1 through DAC8. A one Up indicates the DAC output is active. A zero does not affect the DACs present state. Shutdown individual DAC buffers indicated by data in DAC1 through DAC8. A one Shutindicates the DAC output is down 1 high-impedance. A zero does not affect the DACs present state.
1
1
1
1
0
1
X
X
1
1
1
1
1
0
X
X
Shutdown individual DAC buffers indicated by data in DAC1 through DAC8. A one Shut- indicates the DAC is shutdown down 2 and the output is connected to GND through a 1k resistor. A zero does not affect the DACs present state.
1
1
1
1
0
0
X
X
Shutdown individual DAC buffers indicated by data in DAC1 through DAC8. A one Shut- indicates the DAC is shutdown down 3 and the output is connected to GND through a 100k resistor. A zero does not affect the DACs present state.
X = Don't Care
nected to ground through a 1k or 100k (default) resistor for each DAC. The third shutdown (shutdown 1) command leaves the DACs outputs high impedance. Table 2 lists the three shutdown modes of operation as well as the power-up command.
Serial-Data Output (DOUT)
The DOUT (MAX5306) follows DIN with a 16 clock cycle delay. The DOUT is capable of driving 20pF load with a 50ns (max) delay from the falling edge of SCLK. DOUT is primarily used for daisy-chaining multiple devices. Optionally, DOUT can be used to monitor the serial interface for valid communications by connecting DOUT to a microprocessor input.
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Low-Power, Low-Glitch, Octal 12-Bit VoltageOutput DACs with Serial Interface MAX5306/MAX5307
+5V
SCLK
SK
SS
DIN
SO
DOUT*
MISO*
MAX5306
DOUT*
SI*
MICROWIRE PORT
DIN
MOSI
MAX5307
CS I/O
SCLK
SCK
SPI/QSPI PORT
CS
I/O
*THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5306, BUT MAY BE USED FOR TRANSMISSION VERIFICATION PURPOSES.
CPOL = 0, CPHA = 0 *THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5307, BUT MAY BE USED FOR TRANSMISSION VERIFICATION PURPOSES.
Figure 2. Connections for MICROWIRE
Figure 3. Connections for SPI/QSPI
Hardware Clear (CLR)
The MAX5307 has an active low CLR input. Drive CLR low to clear all internal registers, shutdown all DACs, and terminate all DAC outputs to GND through 100k resistors. CLR is asynchronous and can be applied at any time. If CLR is toggled low during loading of a serial word, that word will terminate and must be reloaded.
Application Information
Daisy-Chaining Devices
Any number of MAX5306 can be daisy-chained by connecting the DOUT pin of one device to the DIN pin of the following device in the chain (Figure 5). To write to the chain, drive CS low until all n x 16 clock cycles (where n is the number of devices in the chain) and associated data have been applied to the first device. When CS is driven high, each device in the chain acts on the 16 bits in its input register. To adjust a single device in the chain, a No-Operation (NOP) command must be loaded for all other devices. Figure 6 shows an alternate method of connecting several MAX5306s or MAX5307s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy chain. More I/O lines are required in this configuration because a dedicated chip-select input (CS) is required for each IC.
Reference Input
The external reference input has a typical input impedance of 200k. The input voltage range is from 800mV to V DD . V DD can be used as the reference for the MAX5306/MAX5307. The DAC outputs are then ratiometric to VDD.
Output Buffer
The rail-to-rail buffer amplifier is stable with any combination of resistive loads greater than 2k and capacitive loads less than 500pF. With a capacitive load of 200pF the output buffers have a slew rate of 1V/s. For a 1/4 FS to 3/4 FS output transition, the amplifier output typically settles to 1/2 LSB in less than 10s when loaded with 2k in parallel with 200pF.
Unipolar Output
The MAX5306/MAX5307 are normally configured for unipolar output. Table 3 lists the unipolar output voltages vs. digital codes.
Power-On Reset
The MAX5306/MAX5307 have a POR circuit to set the DACs output to zero when VDD is first applied. This ensures that unwanted DAC output voltages will not occur immediately following a system startup, such as after a loss of power. Upon initial power-up the POR circuit ensures that all DAC registers are cleared, the DACs are powered-down, and their outputs are terminated to GND through a 100k resistor.
Bipolar Output
The MAX5306/MAX5307 outputs can be configured for bipolar operation using Figure 7's circuit. VOUT = VREF [(2D / 4096 -1)] where D is the decimal value of the DACs binary input code. Table 4 shows digital codes (offset binary) and corresponding output voltages for the Figure 7 circuit.
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Low-Power, Low-Glitch, Octal 12-Bit VoltageOutput DACs with Serial Interface MAX5306/MAX5307
Power-Supply Considerations
On power-up, all input and DAC registers are cleared and DOUT is in low. Bypass VDD to GND with a 4.7F capacitor in parallel with a 0.1F capacitor. Use short lead lengths and place the bypass capacitors as close to the supply pins as possible.
tCL
tCH
SCLK
X
1 tDH tDS
2
3
4
16
X
DIN
X
D15
D14
D13 tSDL tSDH
D12
D1
D0
X
DOUT
X tCSS tCSPWH
D15*
D14*
D13*
D12*
D1*
D0*
X
tCSH
CS
tCLRPWL CLR
*PREVIOUS INPUT DATA
tLDACPWL LDAC
tS 0.5LSB
VOUT_
Figure 4. Timing Diagram
Table 3. Unipolar Code Table
DAC CONTENTS MSB LSB 1111 1111 1111 ANALOG OUTPUT 4095 +VREF ( ------ ) 4096 2049 +VREF ( ------ ) 4096 2048 +VREF +VREF ( ------ )= -------- 4096 2 2047 +VREF ( ------ ) 4096 1 +VREF ( ------ ) 4096 0V
Table 4. Bipolar Code Table
DAC CONTENTS MSB LSB 1111 1000 1000 0111 0000 0000 1111 0000 0000 1111 0000 0000 1111 0001 0000 1111 0001 0000 ANALOG OUTPUT 2047 +VREF ( ------ ) 2048 1 +VREF ( ------ ) 2048 0V 1 -VREF ( ------ ) 2048 2047 -VREF ( ------ ) 2048 2048 -VREF ( ------ )= -VREF 2048
1000
0000
0001
1000
0000
0000
0111
1111
1111
0000 0000 12
0000 0000
0001 0000
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Low-Power, Low-Glitch, Octal 12-Bit VoltageOutput DACs with Serial Interface MAX5306/MAX5307
SCLK SCLK SCLK SCLK
MAX5306
DIN CS DIN CS DOUT DIN CS
MAX5306
DOUT DIN CS
MAX5306
DOUT
TO OTHER SERIAL DEVICES
Figure 5. Daisy-Chaining MAX5306s
DIN SCLK CS1 CS2 CS3 CS CS CS
TO OTHER SERIAL DEVICES
MAX5306 MAX5307
SCLK DIN SCLK DIN
MAX5306 MAX5307
SCLK DIN
MAX5306 MAX5307
Figure 6. Multiple MAX5306s or MAX5307s Sharing a Common DIN Line
Chip Information
VREF R1 REF +5V R2
TRANSISTOR COUNT: 19,000 PROCESS TECHNOLOGY: BiCMOS
MAX5306 MAX5307
DAC OUT
VOUT
-5V R2 = R1
Figure 7. Bipolar Output Circuit
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Low-Power, Low-Glitch, Octal 12-Bit VoltageOutput DACs with Serial Interface MAX5306/MAX5307
Simplified Block Diagram
VDD
CS SCLK DIN SHIFT REGISTER INPUT REGISTERS DAC REGISTERS 12-BIT DAC
OUTPUT BUFFER
OUT1
(MAX5307) CLR (MAX5306) DOUT
INPUT REGISTERS
DAC REGISTERS
12-BIT DAC8
OUTPUT BUFFER
OUT8
LDAC
MAX5306/MAX5307
GND
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Low-Power, Low-Glitch, Octal 12-Bit VoltageOutput DACs with Serial Interface
Package Information
TSSOP,NO PADS.EPS
MAX5306/MAX5307
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA
15
is a registered trademark of Maxim Integrated Products.

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